Design Puzzle: Detection of power of 2 number

Welcome to Design Puzzle. Here we will discuss an interview question:

CDC Analysis using JasperGold

In this post, we will look at the analysis of Clock Domain Crossings in a design using the Cadence JasperGold Tool.

Lint in VLSI using Spyglass

Linting in VLSI is the process of checking the program code (static code analysis) against a set of design rules and generating a report with all details of violations. 

Floating Point Addition / Subtraction

Floating Point Representation in digital systems follows the IEEE-754 format. Let us see how to perform addition / subtraction on floating numbers represented in this format.

FPGA Timing Analysis using Xilinx Vivado

FPGA (Field Programmable Array) consists of the following: Reprogrammable Logic Blocks, Programmable Interconnects and I/O blocks. Let us look at how timing analysis can be performed using Xilinx Vivado Tool.

ASIC Synthesis using Synopsys Design Compiler

Synthesis is defined as the process of converting a synthesizable HDL code into a Gate level netlist using various specifications and parameters obtained from the Design Library.

Restoring Division Verilog Code

 Restoring Division Algorithm is one of the division algorithms used for performing division in digital systems. Let us see how to write the Verilog code for Restoring Division method in FSM format.

Booth Multiplier Verilog Code

Booth's Multiplication Algorithm is a commonly used algorithm for multiplication of two signed numbers. Let us see how to write a Verilog code for this algorithm in an FSM format.

Verilog VPP Switch

In this post, we will see how the verilog vpp file can be used to implement different combinations of defines to generate different designs each time.

SPI Protocol Notes

Serial Peripheral Interface or SPI Protocol is one of the simplest serial protocols used for on-chip communication. 

In this post, we will discuss basic concepts of SPI protocol with some short notes.

Double Flop Synchronizer

When signals move from one clock domain to another, it may not be sampled correctly leading to unstable oscillations in the signal called metastability.

Double Flop Synchronizer or Two flip-flop synchronizer is the simplest synchronization technique to ensure that the signal is sampled correctly at the destination domain.

Memory Addressing and Wrap concepts

Memory Addressing is one of the most fundamental concepts in VLSI and yet, many people get confused when asked simple questions regarding this.

Here, let me cover some important points regarding memory address space, dividing the address space and also basics of wrap concept.

CSR Register operations using APB Protocol

This post is a continuation of the previous post in which the basic structure of CSR Registers were explained.

Here we will look at how reads and writes can be performed on Control and Status Registers using AMBA APB Protocol with Verilog code and explanations.

Control and Status Registers (CSR) Introduction

Control and Status Registers (CSR) are basically a collection of registers present in a system which can be read from/written to by the external device. It is more easily accessible than memories and form an important part of CPUs.

RTL Design Engineer Job Role

In this post I will outline all the job roles and responsibilities that come when donning the role of an RTL Design Engineer in a VLSI Industry.

IP-XACT and Kactus2 Tool

Kactus2 Tool is probably not a very familiar name going around in the VLSI industry. In this post, I will highlight why this tool is required and basics of XML handling using this tool.

Xilinx Vivado Beginner's Guide

In this post, I will give a quick overview of the Xilinx Vivado Tool. It is a successor to the Xilinx ISE Tool and is used for FPGA design.

Xilinx ISE Beginner's Guide

In this post, let's have an overview of the Xilinx ISE Design Suite. This should be a useful tutorial especially for beginners or for anyone who wishes to run through the tool features.

Digital Circuits Practice Questions

Here I have compiled some conceptual questions which have appeared in the GATE exam (ECE) in Digital Circuits or have been discussed by coaching academies.

These are not just for GATE aspirants but for anyone interested in practicing problems. These questions should help you get a fair idea of how to approach problem solving in digital logic.

Fresher Interview Questions

In this post, I've compiled some common questions which are usually asked in interviews for freshers in VLSI. It contains a mix of combinational and sequential logic.

Synchronous FIFO Verilog Code

The First In First Out (FIFO) is a data arrangement structure in which the data that enters first is the one that is removed first. Let us see how to implement Synchronous FIFO in Verilog in this post.

Stack or LIFO Verilog Code

The Last In First Out (LIFO) or Stack is a data arrangement structure in which the data that enters the last is the one that is removed first. Let us see how to implement the concept of Stack using Verilog.

Memory in Verilog

Memory is basically a storage area that can be modelled using Verilog. As we know, a single flip-flop holds a single bit of data. When a number of these flip-flops are combined, we can get a large storage area.

Clock Divider Verilog Code

In this post, we will be implementing a Clock Divider circuit in Verilog. This is one of the most important circuits in VLSI as we can generate one reference clock, and then divide that clock to obtain a number of other slower clocks.

3-Bit Up Counter Verilog Code

A counter is necessary for any timing operation in a design. Let us see how to design a 3-bit counter and then parametrize it to obtain an n-bit counter.

Verilog Tutorial 6: Synthesizable Constructs

This is the sixth part of the Verilog Tutorial series. Click here for the first part.

As discussed before, every piece of Verilog code is written so as to model some hardware component. Our aim is to ensure that we stick to this rule. The code has to be completely synthesizable (to model hardware).

Here we will discuss about all the Synthesizable Verilog constructs.

Verilog Tutorial 5: Modules Instantiation

This is the fifth part of the Verilog Tutorials series. Click here for the first part.

Now we have a fair idea of writing a complete Verilog module from scratch, be it implementing a logic diagram or an FSM. We proceed to how to handle large designs with multiple modules.

Verilog Tutorial 4: The Verilog Testbench

This is the fourth part of the Verilog Tutorials series. Click here for the first part.

Writing a complete Verilog Testbench is no less than an art by itself! A complete Testbench at an industrial level must ensure the complete verification of the designed Verilog code.
It must test the Verilog code with all possible combinations of inputs and the desired outputs must be obtained.

Verilog Tutorial 3: FSM based design

This is the third part of the Verilog Tutorials series. Click here for the first part.

Now let us assume it is not easy to manually design and obtain the complete logic diagram. Then you can implement the Finite State Machine (FSM) directly in Verilog using behavioral modelling. 

This is the primary job of an RTL Design Engineer in a VLSI industry.

Verilog Tutorial 2: Logic Based Design

This is the second part of the Verilog Tutorials series. Click here for the first part.

In the previous tutorial, we discussed about the basic rules of writing a Verilog code.

Let us now write the Verilog code for the Sequence Detector discussed in the Sequential Circuit Design section based on the logic diagram obtained at the end of the design.

Verilog Tutorial 1: Basic Rules

Welcome to Verilog Beginner's Tutorial! In this first post of the tutorial series, I will explain how to write an efficient Verilog code to ensure a stable design. It is assumed that the reader knows the basic terms in Verilog, here I will be dealing with how and when to use them.

Sequential Circuit Design

In this post, we will be learning about Sequential Circuit Design. Asynchronous Sequential circuits suffer from stability issues and are not usually preferred. Hence we restrict our discussion to Synchronous Sequential Circuit Design. This is very similar to the design of a combinational circuit as discussed previously.

Full Adder Verilog Code

Full Adder is used to perform the addition of three 1-bit input data and produces the 1-bit outputs sum and carry out (cout).

Half Adder Verilog Code

Half Adder is one of the simplest combinational circuits which performs the addition of two 1-bit input data and produces the 1-bit outputs sum and carry_out (cout).

D Flip-Flop Verilog Code

D Flip-Flop or Delay Flip-Flop is the fundamental building block for any sequential circuit. Check out how we can code this in Verilog.

Combinational Circuit Design

In this section, I would like to outline the steps to be followed to design any Combinational circuit in a concise manner. Using a combination of basic logic gates (AND, OR, NOT) we can design any Combinational circuit.

8086 Programs: DOS Interrupts

 DOS Interrupt functions can be implemented using Assembly programming.

8086 Programs: Matrix Operations

Matrix addition and matrix multiplication will be performed for 3x3 size using Assembly programming.

8086 Programs: Block Data Operations

Operations on a block of data such as Block Move and Block Exchange is performed using Assembly programming.

8086 Programs: BCD and Hex Number Conversions

16-bit Hex is converted to BCD and 16-bit BCD is converted to equivalent Hex value using Assembly programming.

8086 Programs: Array operations Search and Sort

 Array operations such as searching and sorting using 16-bit values is performed using Assembly programming.

8086 Programs: Basic operations on two BCD Numbers

Basic operations such as addition and subtraction will be performed on two BCD numbers using Assembly programming.

8086 Programs: Basic operations on two 16-bit numbers

Basic operations such as addition and subtraction will be performed on two 16-bit numbers using Assembly programming.