Verilog Tutorial 4: The Verilog Testbench

This is the fourth part of the Verilog Tutorials series. Click here for the first part.

Writing a complete Verilog Testbench is no less than an art by itself! A complete Testbench at an industrial level must ensure the complete verification of the designed Verilog code.
It must test the Verilog code with all possible combinations of inputs and the desired outputs must be obtained.


This is the job of a Verification Engineer in a VLSI Industry. If the desired outputs are not obtained, the designer must make changes to the Verilog code and give it back for verification.

Let us write a simple testbench in Verilog to test the previously discussed Sequence Detector.

Open a new file and write the Verilog Testbench.
1. All inputs are declared as registers (as we must provide values now)
2. All outputs are declared wire (as it is fixed by the design)
3. Instantiate the designed module in the testbench module.
4. Clock signal is written in an always statement as it has to toggle for the entire simulation.
4. Now provide the desired values to the inputs by implementing different techniques and observe the outputs in a simulation waveform.

Let's get back to the sequence counter designed in the previous tutorial.

Testbench:

module seq_detector_tb;

reg clk;     //design inputs are declared reg
reg rst;
reg X;

wire Y;     //design outputs are declared wire

//design module is instantiated
 seq_detector uut (       
  .clk(clk),
  .rst(rst),
  .X(X),
  .Y(Y)
 );

 always #5 clk = ~clk;  //clock signal toggles every 5ns

 initial begin
  $monitor("clk=%b, rst=%b, input=%b, output=%b",clk,rst,X,Y);
  //monitor will print output on console
  //initially device is reset
  clk = 1'b0; 
  rst = 1'b0;                                    
  X = 1'b0;       
  #20 rst = 1'b1;
  //after reset, provide different values for inputs
  #10 X = 1'b0;  #10 X = 1'b1;
  #10 X = 1'b1;  #10 X = 1'b0;
  #10 X = 1'b1;  #10 X = 1'b1;
  #10 X = 1'b1;  #10 X = 1'b1;
  #10 X = 1'b0;  #10 X = 1'b1;
  #10 X = 1'b1;  #10 X = 1'b1;
  #10 X = 1'b0;  #10 X = 1'b0;
  #10 $finish;        //simulation end
 end 

endmodule

Waveform:

Here I have obtained the waveform for the Logic Based design done in Verilog Tutorial 2.

Here I have obtained the waveform for the FSM Based design done in Verilog Tutorial 3.

As expected, in both the waveforms:
When 1 is detected at the input X on three consecutive clock edges (sequence '111'), then the output Y goes high on the third clock edge.

Using tasks and functions:
A testbench can be written using tasks and functions as it simplifies the process of repeatedly executing a set of statements.
Syntax:
task abc (variable1, variable2,... );
..........  //statements using the above variables
endtask

Refer this post: Synchronous FIFO to get an idea of how the testbench uses tasks to call the same operation with different arguments.
Move on to Verilog Tutorial 5 where we will learn about module instantiation to further simplify hardware modelling using Verilog code.