Handshake Synchronizer Design and Verilog Code

In an earlier post, we have seen the usage of a Double Flop Synchronizer. When data has to be sent across from a fast clock domain to a slower domain, Handshake synchronization makes a better choice.

Linear Feedback Shift Register Verilog Code

Linear Feedback Shift Register is used to generate pseudo random numbers. It is used during DFT in VLSI and other applications like DSP. Let us see how to write a Verilog code to design it.

Cache Controller Design Verilog Code

Cache is a small piece of memory present in CPUs used to improve memory access times. Let us see how to design a cache controller in Verilog to control such a cache.

Gated Clock Divider for integral N

Here is a practice question in Verilog where we implement a gated clock divider with the given specifications.

MIPS Processor Design Using Verilog: Part 3

The previous two sections of the Processor Design series explored the intricacies involved in designing a simple MIPS based processor. In this final section, we will look at how the processor can be simulated and how we can check the results.

MIPS Processor Design Using Verilog: Part 2

In Part 1 of the Processor Design series, we saw the descriptions of the individual datapath components of a typical Processor.

In the current Part 2 of the series, let us put them together, generate the Control Unit and understand how the overall processor works.

MIPS Processor Design using Verilog: Part 1

Let us design a simple MIPS based processor and write a Verilog code for it.

Let us first individually examine the typical components of a generic processor and then put them all together to build the complete design of the processor.

ALU design in Verilog using MIPS Instruction Set

MIPS is a RISC (Reduced Instruction Set Computer) based architecture which is used in MIPS based processors.  Let us design a simple ALU in Verilog using few example instructions from the MIPS Instruction Set.

Floating Point Addition / Subtraction

Floating Point Representation in digital systems follows the IEEE-754 format. Let us see how to perform addition / subtraction on floating numbers represented in this format.

Restoring Division Verilog Code

 Restoring Division Algorithm is one of the division algorithms used for performing division in digital systems. Let us see how to write the Verilog code for Restoring Division method in FSM format.

Booth Multiplier Verilog Code

Booth's Multiplication Algorithm is a commonly used algorithm for multiplication of two signed numbers. Let us see how to write a Verilog code for this algorithm in an FSM format.

Double Flop Synchronizer

When signals move from one clock domain to another, it may not be sampled correctly leading to unstable oscillations in the signal called metastability.

Double Flop Synchronizer or Two flip-flop synchronizer is the simplest synchronization technique to ensure that the signal is sampled correctly at the destination domain.

CSR Register operations using APB Protocol

This post is a continuation of the previous post in which the basic structure of CSR Registers were explained.

Here we will look at how reads and writes can be performed on Control and Status Registers using AMBA APB Protocol with Verilog code and explanations.

Stack or LIFO Verilog Code

The Last In First Out (LIFO) or Stack is a data arrangement structure in which the data that enters the last is the one that is removed first. Let us see how to implement the concept of Stack using Verilog.

Synchronous FIFO Verilog Code

The First In First Out (FIFO) is a data arrangement structure in which the data that enters first is the one that is removed first. Let us see how to implement Synchronous FIFO in Verilog in this post.

Memory in Verilog

Memory is basically a storage area that can be modelled using Verilog. As we know, a single flip-flop holds a single bit of data. When a number of these flip-flops are combined, we can get a large storage area.

Clock Divider Verilog Code

In this post, we will be implementing a Clock Divider circuit in Verilog. This is one of the most important circuits in VLSI as we can generate one reference clock, and then divide that clock to obtain a number of other slower clocks.

3-Bit Up Counter Verilog Code

A counter is necessary for any timing operation in a design. Let us see how to design a 3-bit counter and then parametrize it to obtain an n-bit counter.

Full Adder Verilog Code

Full Adder is used to perform the addition of three 1-bit input data and produces the 1-bit outputs sum and carry out (cout).

Half Adder Verilog Code

Half Adder is one of the simplest combinational circuits which performs the addition of two 1-bit input data and produces the 1-bit outputs sum and carry_out (cout).