Double Flop Synchronizer

When signals move from one clock domain to another, it may not be sampled correctly leading to unstable oscillations in the signal called metastability.

Double Flop Synchronizer or Two flip-flop synchronizer is the simplest synchronization technique to ensure that the signal is sampled correctly at the destination domain.

Metastability occurs when the setup/hold time of a flip-flop is violated and it leads to unstable oscillations.

The oscillating signal from the source domain requires some time to settle down (setlling time) and this is what we provide by connecting an extra flip-flop working on the destination clock.

Block diagram:

clk1 → Source clock

clk2 → Destination clock

din → Input signal from source

din_flop → Input signal after one flop

dmeta → Metastable signal

dout → Output signal to destination

Explanation:

1. The input signal from clock domain clk1 is sent to the first flip-flop (launch flip-flop).
2. This signal is flopped and then captured by the second flip-flop (capture flip-flop).
3. The capture flip-flop works on clock domain clk2 and may not capture din_flop correctly. So dmeta may go to a metastable state.
4. The final flip-flop which also works on destination clock will sample dmeta in the next clock cycle and send it as output to the destination. By this time, dmeta would have settled down.

Note:

1. If more time is required for the signal to settle, we can cascade multiple D Flip-Flops working on the destination clock and this becomes a multi-flop synchronizer. However, here we will look only at a double-flop synchronizer.
2. A double flop synchronizer is only useful when the source clock is slower than the destination clock (slow to fast). If the source clock is faster (fast to slow), then source pulse signals can be missed at the destination side and double flop synchronizers will not help. There is a need to explore other synchronization techniques.
3. In fast to slow case itself, we can adjust with double flop synchronizers if we are sure that the input signal will always be active for more than one destination clock period (so that the signal will surely be captured at destination side and we can save hardware resources)
4. Note that double flop synchronizers should only be used to synchronize single-bit signals. For multi-bit signals, we can synchronize a 1-bit enable signal, based on which the multi-bit signal can be sent across. 

Now, let us see the Verilog code for a Double Flop Synchronizer. The signals have been declared as per the block diagram.

Verilog code:

module dfs (
  clk1, //source clk
  clk2, //destination clk
  rst1,
  rst2,
  din,  //input
  dout  //synchronized output
  );

input clk1,clk2,rst1,rst2,din;
output dout;
reg dout, din_flop;
reg dmeta;

always@(posedge clk1 or negedge rst1)
  if(!rst1) din_flop <= 1'b0;
  else din_flop <= din;

always@(posedge clk2 or negedge rst2)
begin
  if(!rst2) 
  begin
    dmeta <= 1'b0;
    dout  <= 1'b0;
  end
  else
  begin 
    dmeta <= din_flop;
    dout  <= dmeta;
  end
end
endmodule

Testbench:

module dfs_tb;

	// Inputs
	reg clk1;
	reg clk2;
	reg rst1;
	reg rst2;
	reg din;

	// Outputs
	wire dout;

	// Instantiate the Unit Under Test (UUT)
	dfs uut (
		.clk1(clk1), 
		.clk2(clk2), 
		.rst1(rst1),
		.rst2(rst2),		
		.din(din), 
		.dout(dout)
	);

always #10 clk1 = ~clk1; 
always #5 clk2 = ~clk2; 

initial
  $monitor($time," clk1=%b, clk2=%b, din=%b, dout=%b, rst1=%b, rst2=%b",clk1,clk2,din,dout,rst1,rst2);

initial
  begin
  clk1=1'b0; clk2=1'b0; din=1'b0; rst1=1'b0; rst2=1'b0;
  #3 rst1=1'b1; rst2=1'b1;
  #17 din=1'b1;
  #60 $finish;
  end
  
endmodule

Simulation Result:

From the waveform, we see that din_flop captures the din value at src clock.

dmeta and dout occur at the next two edges of the destination clock. 

Thus this verifies the Double Flop Synchronizer setup.

We cannot view metastability on a simulator. This is because simulators consider zero setup and hold times for the Flip-flops and so it cannot be violated.

More details on other synchronization techniques can be found here: Verilogpro CDC Series

An interesting question was asked to me during an interview.

Consider a slow source clock of 20 MHz and a fast destination clock of 100 MHz. A single-bit data is passed from source to destination continuously. Is a double-flop synchronizer alone sufficient to obtain accurate data at the destination? 

Normally, we would think yes, what more is required. The data will arrive correctly at the destination.

But a little deeper thought makes you realize that the data arriving at the destination domain will be sampled 5 times faster due to the faster clock.

So what happens is, for example,

If the intended data was just 010, we would end up with the sampled data as 000001111100000.

Now, what is the solution to this problem?

The answer is, you need to use a counter as well. In this case, we need to count till 5 and at every 5th clock alone, we need to sample the data. Only then, data integrity will be maintained.

In a general form, the counter must be able to count upto (Faster clk freq divided by Slower clk freq) number of counts.

So the answer to the question is, we require a Double-Flop Synchronizer along with a counter (to eliminate data repetition due to the faster clock)