Basic Commands for Simulation Tools

A number of EDA tools are used in the VLSI industry for the compilation and simulation of HDL codes. Let us look at the common usage commands for popular EDA tools.

CDC Analysis using JasperGold

In this post, we will look at the analysis of Clock Domain Crossings in a design using the Cadence JasperGold Tool.

Lint in VLSI using Spyglass

Linting in VLSI is the process of checking the program code (static code analysis) against a set of design rules and generating a report with all details of violations. 

FPGA Timing Analysis using Xilinx Vivado

FPGA (Field Programmable Array) consists of the following: Reprogrammable Logic Blocks, Programmable Interconnects and I/O blocks. Let us look at how timing analysis can be performed using Xilinx Vivado Tool.

ASIC Synthesis using Synopsys Design Compiler

Synthesis is defined as the process of converting a synthesizable HDL code into a Gate level netlist using various specifications and parameters obtained from the Design Library.

IP-XACT and Kactus2 Tool

Kactus2 Tool is probably not a very familiar name going around in the VLSI industry. In this post, I will highlight why this tool is required and basics of XML handling using this tool.

Xilinx Vivado Beginner's Guide

In this post, I will give a quick overview of the Xilinx Vivado Tool. It is a successor to the Xilinx ISE Tool and is used for FPGA design.

Xilinx ISE Beginner's Guide

In this post, let's have an overview of the Xilinx ISE Design Suite. This should be a useful tutorial especially for beginners or for anyone who wishes to run through the tool features.