IP-XACT and Kactus2 Tool

Kactus2 Tool is probably not a very familiar name going around in the VLSI industry. In this post, I will highlight why this tool is required and basics of XML handling using this tool.

Kactus2 Tool is used for storage and reuse of electronic circuit designs. The design is described in the form of an IP-XACT syntax based XML file.

IP-XACT is a standard created for simplified integration across EDA tools across multiple vendors. It was established by the SPIRIT consortium (now Accellera)

More information here: https://www.accellera.org/downloads/standards/ip-xact

SPIRIT is an older syntax which is not supported by Kactus2 tool. It supports the IP XACT syntax (IEEE std. 1685-2014)

Here is the User Guide: IP-XACT User Guide

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This post below will cover only how to read and debug an XML file of a design. You can also create designs using this tool but we will not cover that here.

1. Using the IP-XACT syntax, convert your design into an XML File.

2. Check the XML file for syntax and structural errors by using an XML Validation tool. In linux environments, xmllint tool can be used.

(If there are errors in the XML syntax, it may cause your Kactus2 tool to crash)

3. Install the Kactus2 Tool from this website: http://funbase.cs.tut.fi/. You will also find more information and examples in this website.

4. Once your XML file of the design is ready, place it in the Library folder in the installed location of Kactus2 Tool. This will be taken as the default library where it scans IP-XACT based XML files.

5. Run the Kactus2 Tool. The main screen appears as shown.

6. On top, choose Configure Library if you wish to change the library path or include another path.

7. The VLNV tree to the left will have your XML file in the hierarchy. Double click to open the design and press Ctrl + L to unlock the design.

8. Now you can edit various parameters of the design. If anything is shown in red, it means there is an error and it has to be corrected.

For example, here memory_map is having an error because Range is a required field (marked in yellow) which has not been filled. 

9. Check the output screen to ensure there are no errors in your design. If no errors are found, then no error messages are shown. 

10. Now that the design is error-free, there are options for Generating Documentation, Verilog or VHDL code in the Generate Tab.

This is just a basic flow of getting started with the tool. The Help section of the Kactus2 tool will provide you with an extensive coverage of all the capabilities of the tool.