Control and Status Registers (CSR) Introduction

Control and Status Registers (CSR) are basically a collection of registers present in a system which can be read from/written to by the external device. It is more easily accessible than memories and form an important part of CPUs.

In this post, we will see how to model CSR registers using Verilog.

Registers are constructed using flip-flops. To store n-bits of information, we require n flip-flops.

A single register can be divided into multiple fields.

Example: A single ALU status register can be divided into multiple fields to indicate Sign bit, Overflow bit, Parity bit and so on.

Registers (entire register or some fields) can be of the following types:

1. Read/Write (R/W): These registers can be read as well as written from external inputs.

2. Read Only (R): These registers can only be read. Example: Status Registers are used to store the current status information of the hardware. These cannot be changed externally and hence, are usually kept Read Only.

3. Read and clear (RC): Some registers or fields are such that we must clear the content as soon as it is read by the user.

Accessing the registers: 

Each register is characterized by an address in the address space. Consider each register has size 32-bit and starting address of 0x800.

Address of next register = 0x800 + 4 (32-bits = 4bytes) = 0x804

Address of next register = 0x804 + 4 = 0x808, then 0x80C, 0x810 and so on.

After the address is sent, data can be read from/written to the desired register.

Consider the following CSR Registers with the following register descriptions: 

1. DATA_REG (Address: 0x800)

2. STATUS_REG (Address: 0x804)

3. INTERRUPT_REG (Address: 0x808)

Notes:

1. The first register is a Data Register which can either be read or written and consists of 2 fields: data1 and data2 of 10 bits each. The remaining space is Reserved for future and cannot be accessed.
2.  Next one is Status register which holds the status flags of some internal operations. It is modified by the system, so the user can only read it.
3. Next is the Interrupt register. Interrupts are those that inform the user that some action has to be taken based on the status.
• ie suffix here indicates that it is an interrupt enable signal, which indicates that an interrupt must be provided to the user.
• Interrupts are given to inform the user of a particular status condition. Eg. During occurence of overflow, overflow_ie must be set to indicate an overflow interrupt to the user etc.

Let us now see how to read and write to these registers using Verilog in Part 2.