Verilog

Here is a verilog tutorial section that explains how to write Verilog code in the most simplest and practical manner.
Verilog Tutorial 1: Basic Rules
Verilog Tutorial 2: Logic Based Design
Verilog Tutorial 3: FSM Based Design
Verilog Tutorial 4: The Verilog Testbench
Verilog Tutorial 5: Modules Instantiation
Verilog Tutorial 6: Synthesizable Constructs

Here are a list of commonly designed modules with Verilog codes, testbench, simulation and explanations:

Note that all the below codes are completely synthesizable.

Level-1 Verilog codes

1. D Flip-Flop 

2. Half Adder

3. Full Adder
4. Up-Counter
5. Clock Divider
6. Memory

7. Double Flop Synchronizer

8. Handshake Synchronizer

9. Linear Feedback Shift Register

Level-2 Verilog Codes

1. Stack or LIFO
2. Synchronous FIFO

3. CSR Registers operation using APB 

4. Booth Multiplication

5. Restoring Division

6. Floating Point Addition / Subtraction

7. ALU design using MIPS Instruction Set
8. Cache Controller Design

Simple MIPS Processor Design Using Verilog 

MIPS Processor Design Part 1

MIPS Processor Design Part 2

MIPS Processor Design Part 3

Verilog Practice:

Gated Clock Divider with any integer N

Verilog/VHDL are regarded as HDLs or Hardware Descriptive Languages. They are essentially used to model digital hardware designs.

Verilog modelling methods:

1. Gate-level modelling:  This is the lowest level of modelling that directly deals with logic gates using pre-defined gate models.
2. Dataflow Modelling: This method makes use of operators to obtain the desired operation of the logic circuit based on their function.
3. Behavioural Modelling: This method uses an algorithmic approach to obtain the desired logic circuit and makes use of statements like if-else, case etc.

An ideal digital designer is one who can completely design the circuit (Combinational/Sequential) by following the design steps, model the circuit in a HDL like Verilog and simulate the circuit to ensure correct operation.

For purely Combinational circuits, Gate-level modelling is ideal, if not go for Dataflow.

For complex designs that include Combinational as well as Sequential circuits, Behavioural modelling is the preferred mode due to its algorithmic style.

Main differences between Verilog and programming languages:

1. Verilog statements do not execute from top to bottom. All statements execute at the same time unless there is an always block with specific conditions.
2. Verilog coding is not just about getting the output. It is about how much of hardware resources have been consumed to obtain that output. Hence the code must be as compact as possible to avoid excess hardware usage.