Half Adder Verilog Code

Half Adder is one of the simplest combinational circuits which performs the addition of two 1-bit input data and produces the 1-bit outputs sum and carry_out (cout).


Function: Addition of two 1-bit inputs

Truth Table:

X	Y	SUM	COUT
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Schematic:

Verilog Code:

module Half_Adder(sum,cout,x,y);
input x,y;
output sum, cout;
wire sum, cout;

assign sum = x ^ y;
assign cout = x & y;

endmodule

Testbench:

module Half_Adder_tb;
 reg x;
 reg y;
 wire sum;
 wire cout;

 Half_Adder uut (
  .sum(sum),
  .cout(cout),
  .x(x),
  .y(y)
 );

initial begin
 x = 0; y = 0;
 #10 x = 0; y = 1;
 #10 x = 1; y = 0;
 #10 x = 1; y = 1;
 #10 x = 0; y = 0;
 end
endmodule

Simulation Result:

Conclusion:

Thus we obtain the sum and carry of the addition of any 2 input data bits.