Full Adder Verilog Code

Full Adder is used to perform the addition of three 1-bit input data and produces the 1-bit outputs sum and carry out (cout).


Function: Addition of three 1-bit inputs.

Truth Table:

A	B	C	SUM	COUT
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	1
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Logic Expression:

SUM  = A'B'C + A'BC' + AB'C' + ABC
           = (A'B' + AB)C + (A'B + AB')C'
           = (A ⊕ B)'C +  (A ⊕ B)C'
           = A ⊕ B ⊕ C

COUT = AB + BC + CA   //This can be obained using K-map reduction
            = AB(C+C') + BC(A+A') + CA(B+B')
            = ABC + ABC' + A'BC + AB'C
            = AB + C(A'B + AB')
            = AB + C(A ⊕ B)

Schematic:











Verilog Code:

module full_adder(a,b,c,sum,cout);
input a, b, c;
output sum, cout;
wire sum, cout;

assign sum = a^b^c;
assign cout = a&b | c&(a^b);

endmodule

Testbench:

module full_adder_tb;
 reg a;
 reg b;
 reg c;
 wire sum;
 wire cout;

 full_adder uut (
  .a(a),
  .b(b),
  .c(c),
  .sum(sum),
  .cout(cout)
 );

 initial begin
  a = 0; b = 0; c = 0;
  #10 a = 0; b = 0; c = 1;
  #10 a = 0; b = 1; c = 0;
  #10 a = 1; b = 1; c = 0;
  #10 a = 1; b = 0; c = 0;
  #10 a = 1; b = 1; c = 1;
  #10 a = 0; b = 0; c = 1;
  #10 a = 0; b = 1; c = 0;
  #10 a = 0; b = 1; c = 1;
 end 
endmodule

Simulation Result:

Conclusion:
Thus the sum and carry out (cout) of the addition of three 1-bit input data have been obtained.

Further steps:
Cascade multiple modules of full adder (FA) in such a way that the carry out of one FA is an input of the next FA. By doing so, we obtain a Ripple Carry Adder.
This structure can be used to add two multi-bit inputs. Number of bits is determined by the number of FA stages connected in cascade.