Verilog Tutorial 2: Logic Based Design

This is the second part of the Verilog Tutorials series. Click here for the first part.

In the previous tutorial, we discussed about the basic rules of writing a Verilog code.

Let us now write the Verilog code for the Sequence Detector discussed in the Sequential Circuit Design section based on the logic diagram obtained at the end of the design.

The logic diagram is reposted here for reference.

Logic Diagram for Sequence Detector

Our aim is to write the verilog code for the above presented logic diagram.

We have a number of gates (combinational) and 2 Flip-flops (sequential)

Let's name A(t +1) as next_A and B(t + 1) as next_B. Other signals can take the same names.
Here we see that next_A, next_B and Y have fixed expressions based on the logic gates (wires).
A and B are outputs of flip-flops (reg). 

Thus, the Verilog code can be written as shown:

Verilog Code:

module seq_det_logic(clk, rst, X, Y);
input clk;                                  
input rst;
input X;
output Y;

reg A, B; 

wire next_A, next_B;
wire Y;

assign Y = A & B;                            //fixed logical expressions
assign next_A = (A | B) & X;
assign next_B = (A | !B) & X;

always @(posedge clk or negedge rst)        //sequential part
begin
 if(!rst)
 begin
 A <= 1'b0;                   //value is 0 during reset
 B <= 1'b0;
 end
 else
 begin
 A <= next_A;
 B <= next_B;
 end
end
endmodule

Once the Verilog code is complete, we must verify the operation using a testbench which will be explained at a later stage of the tutorial.

For complex problems it is not easy to do the complete design and obtain the logic diagram.

Thus after the state diagram step, we implement the state machine directly in verilog using behavioral modelling constructs like if-else or case statements.

We will discuss this in Verilog Tutorial 3.