Digital Circuits Practice Questions

Here I have compiled some conceptual questions which have appeared in the GATE exam (ECE) in Digital Circuits or have been discussed by coaching academies.

These are not just for GATE aspirants but for anyone interested in practicing problems. These questions should help you get a fair idea of how to approach problem solving in digital logic.

Let us look at some mock questions.

1. What is the minimum value of x for the number (13B)x ? (x is the base of the number)

• The maximum digit that a number with base x can have is x-1.
• So this number has digit B, minimum value of x is C.

2. What is the addition of (32)10 and (76)8 ?

• Convert to the same base before doing any operation.
• So (76)8 = (62)10 and then on addition with 32, we get (94)10

3. A bulb has 2 switches, one being at the ground floor and the other at the first floor. The bub can be turned ON or OFF by any one of the switches, leaving the other switch untouched. The logic of the switching of the bulb resembles what gate with the switches as input?

Answer: Here is the truth table. This resembles an XOR Gate.

Sw 1	Sw 2	Output
0	0	0
0	1	1
1	0	1
1	1	0

4. What is the output F(A,B,C,D) of the mux shown in minterms format:

The input variables are A, B, C and D.
A, B, C are present in the select line while D is present in some of the inputs.

• Obtain the Logical expression in terms of all 4 variables
  F = A'B'C'(0) + A'B'C(D) + A'BC'(1) + A'BC(0) + AB'C'(D) + AB'C(D) + ABC'(1) + ABC(0)
     = A'B'CD + A'BC' + AB'C'D + AB'CD + ABC'
• On simplifying, we see D is missing in two minterms.
  Obtain D by multiplying with D + D'
  F = A'B'CD + A'BC'(D + D') + AB'C'D + AB'CD + ABC'(D + D')
     = A'B'CD + A'BC'D + A'BC'D' + AB'C'D + AB'CD + ABC'D + ABC'D'
     = 0011 + 0101 + 0100 + 1001 + 1011 + 1101 + 1100
                              = Σm (3, 4, 5, 9, 11, 12, 13)
• Another variant of this question is they will provide the output and ask us to find the input.

5. What is the output F of this logic circuit?

For this question, simplify the complete logic expression.
Output of AND Gate = A'B' + A'B = A'
Inputs of second decoder are A' and C
Output F = connected to 0th and 2nd pins of decoder
               = (A')'C' + A'C'
               = AC' + A'C'  = C'

• Note: Simplifying logic expressions are common questions in competitive exams. Know how to obtain outputs from individual or cascaded decoders, muxes and logic gates. 
• Also note the pin numbers (instead of 0,1,2,3 as in the decoders above, it can be inverted as 3,2,1,0)

6. What counter is this and how many states does it have? (MSB of counter starts from right-most flip-flop)

Counter Analysis (Quick way)

• First check the clock. It is negative edge triggered. 
• Then check reset. It is negative reset, meaning the counter will start from 000 on reset. So it is an up-counter.
• See the NAND gate. Reset occurs when 0 is fed to the reset pins. 0 output from NAND will occur when both inputs are 1 (count value 110 occurs first)
• So the count sequence is 000, 001, 010, 011, 100, 101, 000 (110 immediately gets reset)
• So number of states is 6.

7. How many states are present in this counter?

The above presented counter cannot be easily analysed as the design in the previous question.This is because we cannot find when the counter will be reset by looking at the diagram.
Go by the traditional method:

• Write the expression for each of the flip-flop inputs:
  J3 = Q2.Q1,   K3 = Q1,   J2 = Q1.Q3',  K2 = Q1,  J1 = K1 = 1
• Draw the state table as shown (start with present state 000, fill the FF inputs using above experssion, then calculate next state based on characteristic table of the flip-flop)
  
  
  

• At 6th clock pulse, we see that the counter will reset (next state is 000). So there are 6 states meaning it is a MOD 6 counter.
  Also, it is a synchronous counter as all flip-flops are triggered simultaneously by the same clock.

8. What is the address range that can be placed on the address lines A0-A15 that will activate the RAM shown in the figure?

To activate the RAM, we need to ensure the following: The decoder is enabled and the line 1 of decoder is active to activate the RAM enable.

• To activate decoder enable, we require the following:
  A11 = A14 = 1 and A10 = A15 = 0
• To select line 1, we need A12 = 0 and A13 = 1.
• Lines A0 - A9 can be of any value ranging from all 0s to all 1s.
  Summarized table (first row is start address and second row is end address):
  
  
  
  
  
• In hex, the address range is 6800 - 6BFF.

9. Consider a 4-bit D/A converter whose analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V. What is the full-scale voltage and analog output for the digital signal 1100?

• Formula to be known: Resolution = VFS / 2^n-1 where VFS is full-scale voltage and n is the number of bits.
• Resolution is the smallest analog output obtained and that is 0.0625V and number of bits is 4. Using this, we get VFS = 15 x 0.0625 = 0.9375 V.
• 1100 corresponds to 12. Multiply it with the resolution to get analog output = 0.75 V.

10. In the following circuit, the comparator output is logic 1 if V+ > V- and is logic 0 otherwise. The D/A conversion is done as per the relation  

                                     VDAC = ∑n=03​2n−1bn

where b3 (MSB), b2, b1 and b0 (LSB) are the counter outputs. The counter starts from the clear state.

What is the stable reading on the LED display?

• Stable reading means we need a constant input to LED. This can occur only if the counter stops counting. To achieve that, we have to get comparator output as 0.
• We need V- greater than V+. To achieve this, we need to find that value of VDAC which just exceeds 6.2V
• Substitute the values of n from 0 to 3 in VDAC expression.
  We obtain: VDAC = 0.5b0 + b1 + 2b2 + 4b3
• Counter output starts from 0000 and increases by 1 every clock pulse. Find VDAC each time.
  
  
  
  
  
• At count value 1101, we see that VDAC has exceeded 6.2V.
• Now to get LED reading, convert 1101 to BCD, so the answer is 13.