Fresher Interview Questions

In this post, I've compiled some common questions which are usually asked in interviews for freshers in VLSI. It contains a mix of combinational and sequential logic.


Combinational and Sequential Logic

1. What is the difference between Latch and Flip-flop?

• Latches are level triggered while Flip-flops are edge triggered.

2. What is Setup and Hold time of a Flip-flop?

• Setup Time is defined as the time before a clock pulse for which the input data must be held stable so that the data can be sampled correctly.
• Hold Time is defined as the time after a clock pulse for which the input data must be held stable so that the data can be sampled correctly.

3. What is the difference between Moore and Mealy state machines?

• Moore state machine output is a function of only the present state.
• Mealy machine output is a function of the present state as well as inputs.

4. What are the types of adders?

• Half Adder (for two 1-bit inputs)
• Full Adder (for three 1-bit inputs)
• Ripple Carry Adder (cascaded FAs)
• Carry Lookahead Adder (reduced delay as compared to Ripple Carry Adder)

5. What are the types of Shift Registers?

• Serial In Serial Out (SISO)
• Serial In Parallel Out (SIPO)
• Parallel In Serial Out (PISO)
• Parallel In Parallel Out (PIPO)

6. What are Ripple Counters and Synchronous Counters?

• In Synchronous counters, all flip-flops are toggled by the same clock simultaneously.
• In Ripple counter, the flip-flops are toggled by different clocks.

7. Design a D Flip-flop using a T Flip-flop.

• For this kind of question, we need the excitation table of the available flip-flop (D) and characteristic table of the required flip-flop (T).
• They are combined into a single table as shown:

Present state Q(t)	Available FF input (T)	Next state Q(t+1)	Required FF input (D)
0	0	0	0
0	1	1	1
1	0	1	1
1	1	0	0

• Now we must find the expression for D in terms of inputs Q(t) and T.
• Then we get: D = Q(t) ⊕ T
• Logic Diagram:

8. Implement different 2-input logic gates using 2:1 Mux.

• Let the 2 inputs be A and B. Let A be the select of the Mux and B be another input.
• Let's do for AND gate, other gates follow same procedure. Draw its truth table.

A	B	OUT
0	0	0
0	1	0
1	0	0
1	1	1

• When select A is high, out is B. When select A is low, out is 0.
• Now make this connection to the Mux.
• Diagram:

9. Implement 4:1 Mux using 2:1 Mux.

• Number of inputs is 4. So we need two 2:1 muxes at the input side.
• Output is 1. Just connect as shown to satisfy desired inputs and outputs.
• Similarly other muxes can be realized using multiple 2:1 muxes.

10. Given an input signal, how to generate one pulse of the input signal?

• One pulse means we must generate the input (in) for just one clock period.
• Procedure: Delay the input by one clock period (in_d)
• pulse = in & !in_d is the required logic.

11. How many flip-flops are required to construct a MOD-7 counter?

• MOD-n counter has a total of n counts. So MOD-7 counter counts from 0 to 6 (7 counts)
• Maximum count is 6 ⇒ 3 bits required to represent it ⇒ 3 flip-flops required.

12. For a MOD-4 up counter starting from 0, what will be the count value after 1569 clock pulses?

• MOD-4 counter can have only 4 counts (0,1,2,3) After every 4th clock pulse, it resets back to 0.
• Divide 1569 by 4, we get a remainder of 1.
• So after 1569 clock pulses, the count value will be 1.