Verilog VPP Switch

In this post, we will see how the verilog vpp file can be used to implement different combinations of defines to generate different designs each time.

The Verilog VPP file is called the Verilog Preprocessor.

In order to incorporate switches in your Verilog code based on compiler directives like `define conditions, we can use .vpp files.

The VPP file will contain your RTL code with all conditions of `define using constructs like `ifdef, `else and `endif. Example: main.vpp

The desired switch configuration should be present in a file (say config.vpp) with the required define condition enabled. This file should be included in main.vpp file. (`include "config.vpp")

Now you have to generate the Verilog file (.v) based on the desired `define condition by the vpp command by executing a shell script.

(Or the command can be issued directly)

How to execute a shell script:

1. To create an executable script, create a file eg. gmake with extension .sh
2. On top of the file, mention the path of the csh.
   Eg. #!/bin/csh -f
3. To convert main.vpp to main.v, your gmake file should contain the following syntax:
   vpp main.vpp > main.v
4. To provide required permissions to make your file executable, run the following command   
   chmod +x gmake.sh
5. To execute the gmake file, type the following command in the current directory
   ./gmake.sh
6. Now the Verilog file with .v extension will be generated with only the specified `define condition (in config.vpp) present in it.

Example:

Contents of config.vpp:

`define option1 = 1
`define option2 = 0

Contents of main.vpp:

`include "config.vpp"
module main;
 reg a;
always @ *
 begin
`ifdef option1
 a = 1'b1;
`else
 a = 1'b0;
`endif
end
endmodule

After the vpp process, the generated main.v file would look like this:

module main;
 reg a;
always @ *
 begin
 a = 1'b1; 
 end
endmodule

(Only the statements under the implemented branch will be visible)