Clock Divider Verilog Code

In this post, we will be implementing a Clock Divider circuit in Verilog. This is one of the most important circuits in VLSI as we can generate one reference clock, and then divide that clock to obtain a number of other slower clocks.

3-Bit Up Counter Verilog Code

A counter is necessary for any timing operation in a design. Let us see how to design a 3-bit counter and then parametrize it to obtain an n-bit counter.

Verilog Tutorial 6: Synthesizable Constructs

This is the sixth part of the Verilog Tutorial series. Click here for the first part.

As discussed before, every piece of Verilog code is written so as to model some hardware component. Our aim is to ensure that we stick to this rule. The code has to be completely synthesizable (to model hardware).

Here we will discuss about all the Synthesizable Verilog constructs.

Verilog Tutorial 5: Modules Instantiation

This is the fifth part of the Verilog Tutorials series. Click here for the first part.

Now we have a fair idea of writing a complete Verilog module from scratch, be it implementing a logic diagram or an FSM. We proceed to how to handle large designs with multiple modules.

Verilog Tutorial 4: The Verilog Testbench

This is the fourth part of the Verilog Tutorials series. Click here for the first part.

Writing a complete Verilog Testbench is no less than an art by itself! A complete Testbench at an industrial level must ensure the complete verification of the designed Verilog code.
It must test the Verilog code with all possible combinations of inputs and the desired outputs must be obtained.

Verilog Tutorial 3: FSM based design

This is the third part of the Verilog Tutorials series. Click here for the first part.

Now let us assume it is not easy to manually design and obtain the complete logic diagram. Then you can implement the Finite State Machine (FSM) directly in Verilog using behavioral modelling. 

This is the primary job of an RTL Design Engineer in a VLSI industry.

Verilog Tutorial 2: Logic Based Design

This is the second part of the Verilog Tutorials series. Click here for the first part.

In the previous tutorial, we discussed about the basic rules of writing a Verilog code.

Let us now write the Verilog code for the Sequence Detector discussed in the Sequential Circuit Design section based on the logic diagram obtained at the end of the design.

Verilog Tutorial 1: Basic Rules

Welcome to Verilog Beginner's Tutorial! In this first post of the tutorial series, I will explain how to write an efficient Verilog code to ensure a stable design. It is assumed that the reader knows the basic terms in Verilog, here I will be dealing with how and when to use them.

Sequential Circuit Design

In this post, we will be learning about Sequential Circuit Design. Asynchronous Sequential circuits suffer from stability issues and are not usually preferred. Hence we restrict our discussion to Synchronous Sequential Circuit Design. This is very similar to the design of a combinational circuit as discussed previously.

Full Adder Verilog Code

Full Adder is used to perform the addition of three 1-bit input data and produces the 1-bit outputs sum and carry out (cout).

Half Adder Verilog Code

Half Adder is one of the simplest combinational circuits which performs the addition of two 1-bit input data and produces the 1-bit outputs sum and carry_out (cout).

D Flip-Flop Verilog Code

D Flip-Flop or Delay Flip-Flop is the fundamental building block for any sequential circuit. Check out how we can code this in Verilog.

Combinational Circuit Design

In this section, I would like to outline the steps to be followed to design any Combinational circuit in a concise manner. Using a combination of basic logic gates (AND, OR, NOT) we can design any Combinational circuit.