Handshake Synchronizer Design and Verilog Code

In an earlier post, we have seen the usage of a Double Flop Synchronizer. When data has to be sent across from a fast clock domain to a slower domain, Handshake synchronization makes a better choice.

Low Power RTL Design

As we move into lower process nodes over the years, reduction of power is becoming a critical factor during chip design along with reduction of area. Low power design techniques at the RTL level can significantly help to manage power requirements. 

Linear Feedback Shift Register Verilog Code

Linear Feedback Shift Register is used to generate pseudo random numbers. It is used during DFT in VLSI and other applications like DSP. Let us see how to write a Verilog code to design it.

SystemVerilog Sample Testbench Environment

Let us see how we can create a simple testbench environment using SystemVerilog. This will help to get familiar with the usage of SystemVerilog to create a simple testbench.

SystemVerilog Reference Sheet

Here is a quick reference sheet for SystemVerilog concepts which includes definition, syntax and examples. This should be helpful to refresh the basic SV concepts for interviews. 

Cache Controller Design Verilog Code

Cache is a small piece of memory present in CPUs used to improve memory access times. Let us see how to design a cache controller in Verilog to control such a cache.

Perl File Handling Examples

Here are some Perl examples that involves file I/O operations.