Here is a quick reference sheet for SystemVerilog concepts which includes definition, syntax and examples. This should be helpful to refresh the basic SV concepts for interviews.
SYSTEMVERILOG
1. Data Types
Bit , Byte (8 bits)
Logic, reg, wire
Int - shortint (16 bits), int (32 bits), longint (64 bits)
Arrays:
- Static (packed format: [1:0][1:0]array and unpacked format: [1:0]array[1:0])
- Dynamic - [ ] array - no
width given initially
Can be modified using new[], size() and delete() functions. - Associative - array [index_type]
index_type can be of any type and not just integers. - Queues - queue [$]
Example functions used with queue: push_back, pop_front
Structures: (can be packed or unpacked)
struct {
[list of variables]
} struct_name
A packed structure can be accessed
by a single vector while unpacked structure needs to be accessed using
individual fields.
Typedef causes creation of a
user-defined data type.
Syntax: typedef [ enum | struct | union | class ] type_identifier
2. Function and Task
Function does not consume
simulation time and cannot have time controlled events.
Pass by value (default)
Pass by reference - keyword: ref
Automatic tasks – memory allocated is separate for each task call,
meaning multiple overlapping task calls will not interfere with each other.
Global tasks have global scope
3. Threads or Processes
Threads execute as separate entity within
a process but they share same memory space.
Eg. initial block, always block, multiple begin-end statements within fork-join
are all separate threads.
Processes are provided unique
memory spaces/resources. So processes do not interfere with each other. Eg. Different
fork-joins are different processes.
fork-join exits only after all threads are complete
fork join_any (exits after completing any one thread)
fork join_none (immediate exit)
disable_fork to force stop the fork-join execution
wait_fork waits until all fork-joins are over.
4. Interprocess Communication
Special resources to communicate
between processes (by default, each process is independent)
Eg. Events, Semaphores, Mailbox.
4.1 Events
Event is a static object handle to
synchronize between two or more currently active processes.
Trigger event using -> operator
Eg. @(posedge valid) -> event_name
Then wait for event using @ operator or .triggered (to avoid race condition)
Eg. @(event_name)
4.2 Semaphore
A semaphore key allows access to a
shared resource one at a time.
Example:
semaphore key;
key = new(1); //1 represents number
of keys
key.get (1); //get the key
(resource is blocked)
key.put(1); //put the key
(resource is now available)
5. Mailbox
Data transfer channel between two
components.
Put data using mbx.put() and get
data using mbx.get() where mbx is a mailbox handle
6. Interface
A group of signals are bundled within
an interface-endinterface block.
The direction of the signals is
indicated by modport and all modports
for that interface are present within the interface block.
Signals in an interface object are
accessed using format: interface_object.signal
virtual interface is a
pointer to an actual interface. It is used in tb environment to pass signals
between tb components.
Syntax: virtual interface_name
instance_name
6.1 Clocking Blocks
Signals within a clocking block
will be sampled/driven with respect to that clock.
It is helpful when you want to
sample/drive signals after a specified time delay. This can be specified using default.
## operator is used to delay
execution for specified no of clock cycles
##2 is same as repeat(2) @ posedge clk
7. Class
Encapsulates signals,
tasks/functions under a common block.
Declared within class and endclass keywords.
new () function is a constructor, to initialize values
this keyword is used to refer to variables within the current
class.
Eg. class abc
//details
endclass
abc abc_obj1, abc_obj2; //class handles
abc_obj1 = new ( ) //note that class object is created only after calling
constructor. O
Accessing fn: abc_obj.fn_name ( ) //function is also called method
Inheritance: Derived class can be created using extends keyword.
Eg. class base extends derived
super keyword is used to call
functions of base class.
By default, all class members have public scope.
Abstract class: virtual keyword creates an abstract
class, cannot create object for abstract class.
A virtual method inside abstract class is called pure virtual
method.
Consider two handles: From base
class bc and derived class sc
bc = sc is allowed but sc = bc is not allowed
Virtual method: virtual
function creates a virtual method which enables all child classes to
override the base class method definition. So each child class can have a
different function definition.
This is the base for Polymorphism. Same function name and arguments
but different function definition based on the object.
Static variable: A static variable is one where the same
copy of the variable is shared between all class objects.
Static method:
Can be called outside the class,
called using :: operator
Cannot access non-static members
Cannot be virtual
Shallow copy: obj2 = obj1
Deep copy: obj2.copy (obj1)
8. Constraints
Randomization: variables are declared as rand (random) or randc
(cyclic, repeats only after one cycle of values are completed). Use randomize ( ) to call the variable.
Constraints are used to restrict
the values of random variables.
Format: constraint constraint_name {variable inside [5:10]}
Common constraints used:
Relational operators (<, >)
inside [upper_limit : lower_limit] and !inside
dist for weighted distributions (:= to specify weight)
Eg. 0:=10 means there is 10/(total chance) of picking value 0
Static constraints: shared across all class instances
9. Assertions
SV Assertions are used to perform
Formal Verification. In this method, testbenches are written in the following
fashion:
Inputs to DUT are constrained
using assume directive
Required checks are made using assert conditions
Obtain functional coverage using cover property
Types: Immediate and Concurrent
Immediate Assertion: similar to if
assertion_name:
assert (current state !=0)
Concurrent Assertion
Keyword: property
Format 1:
assert property (
@(posedge clk) disable iff (rst)
req | -> ##3 ack
)
Format 2: named property block
property PropName;
@ (posedge clk) disable iff (rst)
req | -> ##3 ack
endproperty
AssertionName: assert property (PropName);
The above assertions checks if ack arrives 3
clocks after req is made, else an error is reported.
## measures delay as number of clock cycles.
| => can be used to evaluate RHS one clock
cycle after LHS is true
Complex properties are built using sequences
sequence request Req; endsequence
sequence acknowledge ##[1:2]; Ack endsequence
property handshake; @(posedge clk) request |-> acknowledge;
assert property (handshake);
SVA consists of many system functions and
operators which needs to be looked at.
10. Coverage
Two types: Functional coverage and code
coverage.
Code coverage examines how much DUT code has
been exercised in the testbench.
Functional coverage can be done in SystemVerilog
using covergroup.
The variables to be covered come under coverpoint.
For each coverpoint, we have bins that indicate unique values (or
features).
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