Low Power RTL Design

As we move into lower process nodes over the years, reduction of power is becoming a critical factor during chip design along with reduction of area. Low power design techniques at the RTL level can significantly help to manage power requirements. 

Introduction

Total Power dissipation for a CMOS cell is given by the sum of Switching power (Dynamic), Leakage power (Static) and Short-circuit power.

Static/Leakage power dissipation occurs when the CMOS is in idle state. It is usually governed by the manufacturing process and not much controllable by front end design.

Lower threshold voltage (VT) transistors would cause higher leakage power dissipation.
But increasing the threshold voltage would increase the voltage required to turn on the transistor thereby increasing Dynamic power dissipation, so a tradeoff is required.

Dynamic/Switching power dissipation occurs when the transistors switch between off and on states, thereby causing charge-discharge cycles on the output load capacitor. 

The switching power dissipation is given by:
P = alpha *Cs * V^2 * f.

where:

alpha is the activity factor

Cs is the switching load capacitance

V is the supply voltage

f is the operating frequency

From here, we find that power reduces linearly with reduction in frequency, capacitance and quadratically with reduction in supply voltage. 

However this reduction in f or V could affect the design performance as the design will be able to run only at lower speeds. Hence it is important to reach the optimum trade-off depending on the chip.

Power Management Techniques

Let us look at some of the techniques which can be followed to help power reduction at RTL level.

1. Clock Gating

The clock is the signal with highest switching activity and so becoming the major contributor of power dissipation of any chip. 
The simplest thing that can be done is to cut off the clock whenever it is not required to be used.

As shown above, the clk signal is gated off with enable. So the clock is turned on only when enable is high.

However, this AND gate will not be glitch-free.

Hence, many standard cell libraries have started supporting a dedicated clock gating cell for this purpose. 

Here is a site that explains about the clock gating cell:
http://vlsi-soc.blogspot.com/2012/08/clock-gating-integrated-cell.html

2. Power Gating

Power Gating or Power collapse is the process of turning off the power supply for sections of logic which are not required to be used at that time.
This is highly effective in power reduction but the power down and re-power up needs to be performed in proper sequence to avoid damage to the chip.

State retention elements are required to ensure that data which requires to be retained are not lost, and value is restored upon power-up.

Eg. Retention elements would be special low power flip-flops.

We also require Isolation logic to prevent the interaction of powered-off logic with the on-logic. Otherwise it would result in X-propagation causing chip damage.

Eg. The simplest isolation cell could be just an AND gate with an isolation enable input.

3. Dynamic Voltage and Frequency Scaling (DVFS)

This refers to change of voltage and frequency proportionally on the fly, depending on design requirement.

This helps to conserve power at different times but must be done carefully to ensure that performance is not degraded.

Reduction in frequency directly affects design speed. Reduction in voltage causes the MOS transistors to take more time in switching hence, indirectly affects design speed. Out of the two, reduction in voltage is more effective in reducing power due to its quadratic relationship with dynamic power.

4. Multiple Supply Voltages

For portions of logic where reduced power is enough, we can work with reduced supply voltage.
Though active power is reduced, it causes reduction in design performance as well.
Also level shifter is required when crossing across power domains.

5. Constant Inputs on inactive logic

During inactive state of an enable signal, the input signals that are dependent on the enable can be forced to a constant value.

This reduces dynamic power dissipation as switching activity is reduced.

Unified Power Format

UPF is a format for describing the power intent of a design. 

RTL + UPF is provided for synthesis.

These are the basic steps followed:

• Define the power architecture: power domains, rails and switches.
• Create power tables
• Add required power elements: Isolation cells, Retention cells, Level shifters, Power switches.
• Isolation (Isolation of power gated domain of a circuit from the ON domain)
• Retention (preserving memory values during power down state)
• Level shifters (translates signal values to traverse across different power domains)
• Power switches (to activate or shut-down the power using ON/OFF control)

UPF Commands

These are various common UPF commands along with arguments in brackets. 

• set_design_top and set_scope (to refer another instance)
• create_power_domain (-elements, -include_scope, -scope) for collection of instances that are power managed the same way.
• create_supply_port (-domain, -direction) for power, ground, nwell and associate with power domain
• create_supply_net (-domain, -reuse) to associate to a power domain and connect_supply_net (-ports, -pins) to connect to the port.
• set_domain_supply_net is used to specify primary power net and ground net for a particular power domain.
• load_upf for sub blocks.
• All sub-blocks having create_supply_port will have a connect_supply_net at top level.
• create_power_switch (-domain, -output_supply_port, -input_supply_port, -control_port, -on_state, -off_state). The control signal for the power switch must already be present in the HDL description.
• supply_port_state: add_port_state (-state) to add the OFF and ON state for ports.
• The legal combination of OFF and ON states is provided by the Power State Table.
• Power State Table:
• Created using create_pst (creates header of table) and add_pst_state (each row of table)
• set_retention (-domain, -retention_power_net, -retention_ground_net, -elements) and set_retention_control (-domain, -save_signal, -restore_signal)
• set_isolation (-domain, -applies_to, -clamp_value, -isolation_power_net, isolation_ground_net) and set_isolation_control (-domain, -isolation_signal, -isolation_sense, -location)
• set_level_shifter (-domain, -threshold, -applies_to, -rule, -location)

Here is a tutorial on Low Power Design and UPF Implementation:
https://www.accellera.org/resources/videos/upf-tutorial-2013