Low Power RTL Design

As we move into lower process nodes over the years, reduction of power is becoming a critical factor during chip design along with reduction of area. Low power design techniques at the RTL level can significantly help to manage power requirements. 

Linear Feedback Shift Register Verilog Code

Linear Feedback Shift Register is used to generate pseudo random numbers. It is used during DFT in VLSI and other applications like DSP. Let us see how to write a Verilog code to design it.

SystemVerilog Sample Testbench Environment

Let us see how we can create a simple testbench environment using SystemVerilog. This will help to get familiar with the usage of SystemVerilog to create a simple testbench.

SystemVerilog Reference Sheet

Here is a quick reference sheet for SystemVerilog concepts which includes definition, syntax and examples. This should be helpful to refresh the basic SV concepts for interviews. 

Cache Controller Design Verilog Code

Cache is a small piece of memory present in CPUs used to improve memory access times. Let us see how to design a cache controller in Verilog to control such a cache.

Perl File Handling Examples

Here are some Perl examples that involves file I/O operations.

Perl Basic Examples

Let us learn Perl the practical way with some examples that will help to understand the usage of different commands and constructs in Perl.

Perl Commands: Reference Sheet

Here are some important Perl commands and constructs that are commonly used in Perl scripts to serve as a reference.

Gated Clock Divider for integral N

Here is a practice question in Verilog where we implement a gated clock divider with the given specifications.

MIPS Processor Design Using Verilog: Part 3

The previous two sections of the Processor Design series explored the intricacies involved in designing a simple MIPS based processor. In this final section, we will look at how the processor can be simulated and how we can check the results.

MIPS Processor Design Using Verilog: Part 2

In Part 1 of the Processor Design series, we saw the descriptions of the individual datapath components of a typical Processor.

In the current Part 2 of the series, let us put them together, generate the Control Unit and understand how the overall processor works.

MIPS Processor Design using Verilog: Part 1

Let us design a simple MIPS based processor and write a Verilog code for it.

Let us first individually examine the typical components of a generic processor and then put them all together to build the complete design of the processor.

ALU design in Verilog using MIPS Instruction Set

MIPS is a RISC (Reduced Instruction Set Computer) based architecture which is used in MIPS based processors.  Let us design a simple ALU in Verilog using few example instructions from the MIPS Instruction Set.