Basically, an RTL Design Engineer will be expected to perform the following tasks:
1. RTL Programming
2. Microarchitecture Building
3. RTL Optimization
4. Lint violations check
5. CDC check
6. Synthesis Check
7. Creation of Testbenches
8. Dump Analysis - Running, viewing and debugging
9. Static Timing Analysis
10. Scripting (TCL/Perl)
Let us go over each of the above points:
1. RTL Programming
Depending on the company, an RTL Design Engineer is expected to master a Hardware Modelling Language like Verilog or VHDL.
Ensure that you know the complete syntax as well as usage of the language in practical scenarios.
2. Microarchitecture Building
Microarchitecture means completely describing the operation of the designed hardware in the form of a documentation with relevant block diagrams, figures and explanations. It must act like a user guide for new users.
3. RTL Optimization
As we know, the main aim of using a HDL like Verilog is not just to obtain the desired output but to minimize the hardware resource usage by shortening the code as much as possible.
An RTL Design Engineer must be able to visualize the logic circuit for every piece of code that is being developed and ensure that the most optimized and simple logic is being used.
In some cases, even the compiler will perform some optimizations.
4. Lint violations check
During RTL compilation, syntax errors are detected. Linting is a process in which structural errors and clock domain crossing issues are detected as well. Cadence HAL/Sysnopsys Spyglass are commonly used tools.
5. CDC Check
Clock Domain Crossing issues are the most troublesome issues for Digital Designers. When working with multiple clocks, utmost care must be taken to ensure that signals crossing from one clock domain to another are synchronized properly. Synopsys Spyglass/ Cadence Jaspergold are commonly used tools for CDC checks.
6. Synthesis Check
Synthesis is the process in which the HDL code is simplified into a gate-level representation and a Netlist file is generated.
For ASIC synthesis, tools like Synopsys Design Compiler or Cadence Genus can be used whereas for FPGA synthesis, Xilinx Vivado Tool is commonly used.
One has to ensure that the HDL code is completely synthesizable, ie., every piece of code must be able to translate into a hardware component.
7. Creation of Testbenches
An RTL Design Engineer is expected to know the basics of creating testbenches to verify the design. Though more rigorous verification methods are carried out by the Verification Team, a Design Engineer must be able to create simple testbenches using SystemVerilog to verify the basic operations of the design.
8. Dump Analysis - Running, viewing and debugging
Dump refers to waveform simulations of the design. After completing the design, the verification team will provide the simulation waveform to the designer which can be checked for correct operation. If there are errors, 'bugs' are filed which must be corrected by the design engineer.
9. Static Timing Analysis
This is one of the most important concepts of VLSI and it is imperative that design engineers must code in such a way that timing requirements are satisfied in the overall design. This is a big topic in itself and we will not discuss it here.
10. Scripting (TCL/Perl)
The knowledge of scripting languages like TCL or Perl is not a necessary requirement in the initial stages but is always an additional bonus to the skill set. It can be used to simplify many operations that would otherwise be time consuming and helps in automation.
Hopefully, this post has provided an overview of the roles that are expected by a design engineer in the VLSI industry. This will provide a fair idea of the job requirement but it cannot be said that the job is limited to these roles alone.
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