Xilinx Vivado Beginner's Guide

In this post, I will give a quick overview of the Xilinx Vivado Tool. It is a successor to the Xilinx ISE Tool and is used for FPGA design.

Xilinx ISE Beginner's Guide

In this post, let's have an overview of the Xilinx ISE Design Suite. This should be a useful tutorial especially for beginners or for anyone who wishes to run through the tool features.

Digital Circuits Practice Questions

Here I have compiled some conceptual questions which have appeared in the GATE exam (ECE) in Digital Circuits or have been discussed by coaching academies.

These are not just for GATE aspirants but for anyone interested in practicing problems. These questions should help you get a fair idea of how to approach problem solving in digital logic.

Fresher Interview Questions

In this post, I've compiled some common questions which are usually asked in interviews for freshers in VLSI. It contains a mix of combinational and sequential logic.

Synchronous FIFO Verilog Code

The First In First Out (FIFO) is a data arrangement structure in which the data that enters first is the one that is removed first. Let us see how to implement Synchronous FIFO in Verilog in this post.

Stack or LIFO Verilog Code

The Last In First Out (LIFO) or Stack is a data arrangement structure in which the data that enters the last is the one that is removed first. Let us see how to implement the concept of Stack using Verilog.

Memory in Verilog

Memory is basically a storage area that can be modelled using Verilog. As we know, a single flip-flop holds a single bit of data. When a number of these flip-flops are combined, we can get a large storage area.