Design Puzzle: Detection of power of 2 number

Welcome to Design Puzzle. Here we will discuss an interview question:

CDC Analysis using JasperGold

In this post, we will look at the analysis of Clock Domain Crossings in a design using the Cadence JasperGold Tool.

Lint in VLSI using Spyglass

Linting in VLSI is the process of checking the program code (static code analysis) against a set of design rules and generating a report with all details of violations. 

Floating Point Addition / Subtraction

Floating Point Representation in digital systems follows the IEEE-754 format. Let us see how to perform addition / subtraction on floating numbers represented in this format.

FPGA Timing Analysis using Xilinx Vivado

FPGA (Field Programmable Array) consists of the following: Reprogrammable Logic Blocks, Programmable Interconnects and I/O blocks. Let us look at how timing analysis can be performed using Xilinx Vivado Tool.

ASIC Synthesis using Synopsys Design Compiler

Synthesis is defined as the process of converting a synthesizable HDL code into a Gate level netlist using various specifications and parameters obtained from the Design Library.

Restoring Division Verilog Code

 Restoring Division Algorithm is one of the division algorithms used for performing division in digital systems. Let us see how to write the Verilog code for Restoring Division method in FSM format.