MIPS Processor Design Using Verilog: Part 3

The previous two sections of the Processor Design series explored the intricacies involved in designing a simple MIPS based processor. In this final section, we will look at how the processor can be simulated and how we can check the results.

MIPS Processor Design Using Verilog: Part 2

In Part 1 of the Processor Design series, we saw the descriptions of the individual datapath components of a typical Processor.

In the current Part 2 of the series, let us put them together, generate the Control Unit and understand how the overall processor works.

MIPS Processor Design using Verilog: Part 1

Let us design a simple MIPS based processor and write a Verilog code for it.

Let us first individually examine the typical components of a generic processor and then put them all together to build the complete design of the processor.

ALU design in Verilog using MIPS Instruction Set

MIPS is a RISC (Reduced Instruction Set Computer) based architecture which is used in MIPS based processors.  Let us design a simple ALU in Verilog using few example instructions from the MIPS Instruction Set.

Design Puzzle: Detection of power of 2 number

Welcome to Design Puzzle. Here we will discuss an interview question:

CDC Analysis using JasperGold

In this post, we will look at the analysis of Clock Domain Crossings in a design using the Cadence JasperGold Tool.

Lint in VLSI using Spyglass

Linting in VLSI is the process of checking the program code (static code analysis) against a set of design rules and generating a report with all details of violations.